An MRAM device is a memory device having a memory unit for storing information using a magnetic effect such as tunneling magneto resistance. When forming the MRAM device, a thin insulating layer having a thickness of about 1000 nm is necessary to insulate a top electrode contact (TEC) for connecting an information storage memory unit and an upper electrode to each other.
FIG. 1 schematically illustrates a related MRAM device.
Referring to FIG. 1, the related MRAM includes transistor devices 15 formed on a semiconductor substrate 10. The semiconductor substrate 10 and the transistor devices 15 are insulated from each other by a lower insulating layer 20. Connection contact structures 30 that penetrate the lower insulating layer 20 are provided in the related MRAM. Also, first metal layers 35 are also provided in the related MRAM. The first metal layers can be electrically connected to the connection contact structures 30. Second metal layers 40 are included on the first metal layers 35. Data lines 45 are used together with the patterns of the second metal layers 40.
The patterns of the second metal layers 40 are electrically connected to the transistor devices 15 by the connection contact structures 30. Lower electrodes 50 are formed on the second metal layers 40. Although not shown, on the lower electrodes 50, an information storage memory unit using a device characteristic is included. An upper electrode 70 including a TiN layer 71 and a third metal layer 75 is formed on the information storage memory unit.
A thin insulating layer 60 made of silicon oxide is formed between the upper electrode 70 and the lower electrode 50 with a thickness between 1,000 to 1,500 nm. The thin insulating layer 60 is used for insulating the top electrode contact (TEC).
FIGS. 2 and 3 schematically illustrate a method of forming a thin insulating layer in a conventional MRAM device.
Referring to FIG. 2, after forming lower patterns 80 such as the lower electrodes and the information storage memory, a first insulating layer 91 can be formed that fills the gaps of the lower patterns 80. The lower patterns 80 include integrated narrow patterns and wide patterns, and the first insulating layer 91 has very low planarization characteristics. In order to planarize the first insulating layer 91, a second insulating layer 93 having better planarization characteristics is formed on the first insulating layer 91. However, the thickness of the entire insulating layer 90 including the first insulating layer 91 and the second insulating layer 93 still vary by region.
A CMP process is performed on the insulating layer 90. Therefore, the insulating layer 90 illustrated in FIG. 3 is planarized. However, in the planarization process, complete local or entire planarization cannot be actually performed. Therefore, when the insulating layer 90 is polished so as to realize a target thickness, the insulating layer becomes severely thin creating an electric short or other defects.
FIGS. 4 and 5 are photographs illustrating the problems with the method of forming thin insulating layer in the related MRAM device.
FIG. 4 is a photograph illustrating the insulating layer having a target thickness and FIG. 5 is a photograph illustrating the insulating layer having a locally thin region, causing a short. As illustrated in FIGS. 4 and 5, according to the related method of forming the thin insulating layer, the insulating layer develops a locally thin region so that the insulating layer cannot be sufficiently insulated from the subsequent metal layers, creating an electrical short or other defect.